A major problem hindering the further size reduction of metal-oxide-semiconductor (MOS) transistor devices is the loss of performance which is characteristic of transistors having channel lengths less than about 0.8 micron. The performance degradation includes but is not limited to low source-drain breakdown voltage, subthreshold leakage, increased junction capacitance and threshold voltage instability. These problems, known collectively as short channel effects, are related to the electrodynamics of the transistor channel during operation. In the scaling of transistor dimensions to smaller values, an attempt is made to adjust the electric field in the channel such that the peak lateral electric field of the drain depletion region is minimized. A widely used technique to reduce the peak lateral field and minimize short channel effects is to fabricate a lightly-doped drain (LDD) structure.
In an N-channel device, a conventional LDD structure comprises an N- region in proximity to the transistor channel and an N+ region displaced away from the channel by the width of the N- region. As the length of the transistor channel is reduced, transistors fabricated using a conventional LDD structure show increased substrate current (ISUB) and lower breakdown voltages (BVDSS). A reduction of the dopant concentration in the N- region improves ISUB and BVDSS however, other parameters such as threshold voltage stability and drive current are degraded because impact ionization and series resistance both increase. The limitations of the conventional LDD structure in preventing performance degradation due to short channel effects in 0.5 micron transistors led to the development of the ITLDD transistor (see for example, T. W. Huang, et al., IEDM Tech. Digest, 1986, p. 742). The ITLDD structure includes a transistor gate having a thin gate extension adjacent to a thick central portion. The gate extension overlaps the N- region and brings the N- region directly within the electric field of the gate. A low series resistance is maintained and hence a high drive current is obtained because the gate extension can effectively accumulate majority charge carriers in the underlying N- region.
While overcoming many of the performance problems in submicron MOS transistors, the ITLDD gate is difficult to fabricate to sub-micron dimensions and short channel effects persist. The short channel effects, particularly threshold voltage instability, are most severe in the case of P-channel devices where the gate is of N-type conductivity. In a CMOS device, the channel region in P-type MOS transistors is typically counter doped to adjust the threshold voltage to slightly lower absolute value. The counter doping results in an active channel region that is well below the substrate surface where lateral drain field encroachment into the channel region is problematic even though an LDD structure has been formed. A transistor having a channel region displaced from the surface of the substrate is known as a "buried channel" device. Lateral drain field encroachment in the buried channel can be reduced, and thus short channel effects minimized, if the energy levels within the gate, represented by the work function potential difference across the gate dielectric (.PHI.), can be adjusted along the length of the ITLDD gate itself.